A shallow trench isolation (STI) structure comprises insulating material which is deposited and patterned on a semiconductor substrate to electrically insulate active components that are formed as part of a FEOL (front-end-of-line) layer on an active surface of the semiconductor substrate. A STI structure is designed to prevent or reduce the flow of leakage current into the semiconductor substrate and to prevent other types of electrical interactions between active devices and components. Semiconductor fabrication process flows typically implement a STI recess process in which an upper surface of a STI layer is recessed before further processing can take place. In semiconductor devices where different patterns of device structures are formed on the semiconductor substrate, recessing the STI layer to a target level is a challenging process because the recess level of the STI layer can vary over the surface of the semiconductor substrate depending on the pattern density of structures in different regions. In particular, the recess level in a given region is dependent on the pattern density of the structures and the amount of space (e.g., pitch) between the structures in the given region. The variation in recess level of a STI layer is due to micro-loading effects of conventional etch processes whereby the STI layer is recessed deeper in regions of the semiconductor substrate having relaxed-pitch structure patterns as compared to regions of the semiconductor substrate having tight-pitch structure patterns. Thus, it is a difficult and non-trivial process to uniformly recess (or etch back) a STI layer on a semiconductor substrate having different densities of structure patterns. The non-uniform recess of a STI layer due to loading effects of conventional etch processes can result in undesired variation in device dimensions, which leads to undesired variation in device performance.